1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device improved in its limited applications.
2. Description of the Background Art
A flash memory capable of erasing an entire memory array at one time (i.e., in a flash) is one of the non-volatile semiconductor memory devices. Flash memories have NOR-type, new-NOR-type and DINOR-type memory cell transistor structures.
FIG. 24 illustrates a program (write) operation of a NOR-type memory cell transistor. FIG. 25 illustrates an erase operation of the NOR-type memory cell transistor. FIG. 26 illustrates a read operation of the NOR-type memory cell transistor. The memory cell transistor shown in FIGS. 24 through 26 has an NMOS structure.
The NOR-type memory cell transistor shown in FIGS. 24 through 26 includes a source main region 41 and a drain region 31 both selectively formed in a surface of a semiconductor substrate 11. A source diffusion region 42 having an impurity concentration lower than that of the source main region 41 is formed around the source main region 41. A floating gate electrode 24 is formed on a portion of the semiconductor substrate 11 lying between the source main region 41 and the drain region 31, with a tunnel oxide film 13 disposed between the semiconductor substrate 11 and the floating gate electrode 24. A control gate electrode 23 is formed on the floating gate electrode 24, with an intergate oxide film 16 therebetween.
A source terminal P1, a drain terminal P2, a gate terminal P3 and a substrate terminal P4 are provided for setting the potential of the source main region 41, the drain region 31, the control gate electrode 23 and the semiconductor substrate 11, respectively.
With such an arrangement, the program operation of the NOR-type memory cell transistor is performed by setting the source terminal P1 at 0 V, the drain terminal P2 at a positive high voltage HV, the gate terminal P3 at the positive high voltage HV, and the substrate terminal P4 at 0 V, as shown in FIG. 24. The above settings cause electrons to be injected into the floating gate electrode 24 because of a channel hot electron phenomenon, whereby the program operation (or the operation of setting the NOR-type memory cell transistor at a high Vth (high threshold voltage)) is performed.
The erase operation of the NOR-type memory cell transistor is performed by setting the source terminal P1 at the positive high voltage HV, rendering the drain terminal P2 floating (or open), setting the gate terminal P3 at 0 V or at a negative high voltage MHV, and setting the substrate terminal P4 at 0 V, as shown in FIG. 25. The above settings cause electrons to be extracted from the floating gate electrode 24 because of an FN (Fowler-Nordheim tunneling) phenomenon near an edge of the source main region 41, whereby the erase operation (or the operation of setting the NOR-type memory cell transistor at a low Vth (low threshold voltage)) is performed.
The read operation of the NOR-type memory cell transistor is performed by setting the source terminal P1 at 0 V, the drain terminal P2 at a positive low voltage HLow, the gate terminal P3 at a read voltage VR (where low Vth less than VR less than high Vth), and the substrate terminal P4 at 0 V, as shown in FIG. 26. The above settings allow detection of whether or not the memory cell transistor enters the on state to identify whether the threshold voltage is high Vth or low Vth, whereby the read operation is performed.
FIG. 27 is a graph showing a distribution of the threshold voltage Vth of the NOR-type memory cell transistor. As shown in FIG. 27, high Vth indicating xe2x80x9c0xe2x80x9d is distributed above 6.0 V, and low Vth indicating xe2x80x9c1xe2x80x9d is distributed between 1.5 V and 3.0 V. As a result, a threshold voltage window width xcex94Vth1 between the high Vth distribution and the low Vth distribution is 2.5 V.
FIG. 28 illustrates a program operation of a new-NOR-type memory cell transistor which is one type of the NOR-type memory cell transistor. FIG. 29 illustrates an erase operation of the new-NOR-type memory cell transistor. FIG. 30 illustrates a read operation of the new-NOR-type memory cell transistor. The memory cell transistor shown in FIGS. 28 through 30 has an NMOS structure.
The new-NOR-type memory cell transistor shown in FIGS. 28 through 30 includes a source region 45 and the drain region 31 both selectively formed in the surface of the semiconductor substrate 11. The floating gate electrode 24 is formed on a portion of the semiconductor substrate 11 lying between the source region 45 and the drain region 31, with the tunnel oxide film 13 disposed between the semiconductor substrate 11 and the floating gate electrode 24. The control gate electrode 23 is formed on the floating gate electrode 24, with the intergate oxide film 16 therebetween.
The source terminal P1, the drain terminal P2, the gate terminal P3 and the substrate terminal P4 are provided for setting the potential of the source region 45, the drain region 31, the control gate electrode 23 and the semiconductor substrate 11, respectively.
With such an arrangement, the program operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P1 at 0 V, the drain terminal P2 at the positive high voltage HV, the gate terminal P3 at the positive high voltage HV, and the substrate terminal P4 at 0 V, as shown in FIG. 28. The above settings cause electrons to be injected into the floating gate electrode 24 because of the channel hot electron phenomenon, whereby the program operation is performed.
The erase operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P1 at the positive high voltage HV, rendering the drain terminal P2 floating (or open), setting the gate terminal P3 at the negative high voltage MHV, and setting the substrate terminal P4 at the positive high voltage HV, as shown in FIG. 29. The above settings cause electrons to be extracted from the floating gate electrode 24 because of the FN phenomenon throughout the channel, whereby the erase operation is performed.
The read operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P1 at 0 V, the drain terminal P2 at the positive low voltage HLow, the gate terminal P3 at the read voltage VR (where low Vth less than VR less than high Vth), and the substrate terminal P4 at 0 V, as shown in FIG. 30, in a similar manner to the NOR-type memory cell transistor.
FIG. 31 is a graph showing a distribution of the threshold voltage Vth of the new-NOR-type memory cell transistor. As shown in FIG. 31, high Vth indicating xe2x80x9c0xe2x80x9d is distributed above 6.0 V, and low Vth indicating xe2x80x9c1xe2x80x9d is distributed between 1.5 V and 3.0 V, as in the NOR-type memory cell transistor. As a result, a threshold voltage window width xcex94Vth2 between the high Vth distribution and the low Vth distribution is 2.5 V.
FIG. 32 illustrates a program operation of a DINOR-type memory cell transistor. FIG. 33 illustrates an erase operation of the DINOR-type memory cell transistor. FIG. 34 illustrates a read operation of the DINOR-type memory cell transistor. The memory cell transistor shown in FIGS. 32 through 34 has an NMOS structure.
The DINOR-type memory cell transistor shown in FIGS. 32 through 34 includes a source region 43 and a drain main region 32 both selectively formed in the surface of the semiconductor substrate 11. A drain diffusion region 33 having an impurity concentration lower than that of the drain main region 32 is formed around the drain main region 32. The floating gate electrode 24 is formed on a portion of the semiconductor substrate 11 lying between the source region 43 and the drain main region 32, with the tunnel oxide film 13 disposed between the semiconductor substrate 11 and the floating gate electrode 24. The control gate electrode 23 is formed on the floating gate electrode 24, with the intergate oxide film 16 therebetween.
The source terminal P1, the drain terminal P2, the gate terminal P3 and the substrate terminal P4 are provided for setting the potential of the source region 43, the drain main region 32, the control gate electrode 23 and the semiconductor substrate 11, respectively.
With such an arrangement, the program operation of the DINOR-type memory cell transistor is performed by rendering the source terminal P1 floating, setting the drain terminal P2 at the positive high voltage HV, setting the gate terminal P3 at the negative high voltage MHV, and setting the substrate terminal P4 at 0 V, as shown in FIG. 32. The above settings cause electrons to be extracted from the floating gate electrode 24 because of the FN phenomenon near an edge of the drain main region 32, whereby the program operation (or the operation of setting the DINOR-type memory cell transistor at low Vth) is performed.
The erase operation of the DINOR-type memory cell transistor is performed by setting the source terminal P1 at the negative high voltage MHV, rendering the drain terminal P2 floating (or open), setting the gate terminal P3 at the positive high voltage HV, and setting the substrate terminal P4 at the negative high voltage MHV, as shown in FIG. 33. The above settings cause electrons to be injected into the floating gate electrode 24 because of the FN phenomenon throughout the channel, whereby the erase operation (or the operation of setting the DINOR-type memory cell transistor at high Vth) is performed.
The read operation of the DINOR-type memory cell transistor is performed by setting the source terminal P1 at 0 V, the drain terminal P2 at the positive low voltage HLow, the gate terminal P3 at the read voltage VR (where low Vth less than VR less than high Vth), and the substrate terminal P4 at 0 V, as shown in FIG. 34, in a similar manner to the NOR-type and new-NOR-type memory cell transistors.
FIG. 35 is a graph showing a distribution of the threshold voltage Vth of the DINOR-type memory cell transistor. As shown in FIG. 35, high Vth indicating xe2x80x9c1xe2x80x9d is distributed above 5.0 V, and low Vth indicating xe2x80x9c0xe2x80x9d is distributed between 1.5 V and 2.0 V. As a result, a threshold voltage window width xcex94Vth3 between the high Vth distribution and the low Vth distribution is 3.0 V.
FIG. 36 is a circuit diagram showing an arrangement of a memory cell array of a NOR-type flash memory. As shown in FIG. 36, memory cell transistors MQ1 are arranged in a matrix such that the (control) gates of memory cell transistors MQ1 in each row are connected to the same word line WL, the drains of memory cell transistors MQ1 in each column are connected to the same bit line BL, and the sources of memory cell transistors MQ1 in each row are connected to the same source line SL while the sources of each pair of memory cell transistors MQ1 adjacent in a column direction are commonly connected. A new-NOR-type flash memory is similar in arrangement of the memory cell array of memory cell transistors to the NOR-type flash memory.
FIG. 37 is a circuit diagram showing an arrangement of a memory cell array of a DINOR-type flash memory. As shown in FIG. 37, memory cell transistors MQ2 are arranged in a matrix such that the gates of memory cell transistors MQ2 in each row are connected to the same word line WL, the drains of a predetermined number of memory cell transistors MQ2 in each column are connected to the source of a select transistor ST having a drain connected to a corresponding bit line BL, and the sources of memory cell transistors MQ2 in each row are connected to the same source line SL while the sources of each pair of memory cell transistors MQ2 adjacent in a column direction are commonly connected.
The above-mentioned NOR-type and new-NOR-type memory cell transistors have a relatively wide distribution of low Vth indicating xe2x80x9c1xe2x80x9d, as shown in FIGS. 27 and 31. This leads to relatively narrow threshold voltage window widths xcex94Vth1 and xcex94Vth2 to create a need for setting the read voltage VR at about 3.0 (V)+xcex1 which is the maximum value of the low Vth distribution, resulting in difficulties in low voltage random access.
On the other hand, the DINOR-type memory cell transistor which is required to identify the write operation for each bit presents difficulties in high-speed write operation such as byte write.
Thus, the NOR-type and new-NOR-type memory cell transistors are not appropriate for low voltage random access applications, and the DINOR-type memory cell transistor is not appropriate for applications which require the high-speed write operation.
It is an object of the present invention to provide a non-volatile semiconductor memory device usable in relatively wide applications, and a method of manufacturing the same.
According to a first aspect of the present invention, the non-volatile semiconductor memory device includes a semiconductor substrate, a first non-volatile memory cell region, and a second non-volatile memory cell region.
The first non-volatile memory cell region is manufactured into the semiconductor substrate and is capable of non-volatile storage. The first non-volatile memory cell region includes a first memory cell transistor having a first operating characteristic in reading, writing and erase operations. The second non-volatile memory cell region is manufactured into the semiconductor substrate and is capable of non-volatile storage. The second non-volatile memory cell region includes a second memory cell transistor having a second operating characteristic different from the first operating characteristic in one of reading, writing and erase operations.
In the non-volatile semiconductor memory device, the regions in which the first and second memory cell transistors, respectively, having different operating characteristics are formed are provided on the single unit of semiconductor substrate. This non-volatile semiconductor memory device produces the effect of being usable in wide applications adaptable to applications of the first and second operating characteristics while ensuring a high level of integration.
Preferably, in the non-volatile semiconductor memory device, the first memory cell transistor includes a NOR-type memory cell transistor, and the second memory cell transistor includes a DINOR-type memory cell transistor.
The non-volatile semiconductor memory device can employ both the NOR-type memory cell transistor capable of high-speed write operation and the DINOR-type memory cell transistor capable of low voltage random access.
Preferably, in the non-volatile semiconductor memory device, the erase operation of the first memory cell transistor includes extracting an electron from a floating gate electrode constituting a memory cell into a surface of the semiconductor substrate serving as a channel region under the floating gate electrode.
The non-volatile semiconductor memory device can employ both the new-NOR-type memory cell transistor capable of high-speed write operation and the DINOR-type memory cell transistor capable of low voltage random access.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.